Verilog Primer

 
  • Chapter1: Introduction to Verilog hardware description language
  • Chapter 2: Verilog Structure
    • 2.1 Modules
    • 2.2 Structural Design with Gate Primitives and the Delay operator
    • 2.3 Structural Design with Assignment Statements
    • 2.4 Structural Design with using Modules
    • 2.5 Behavioral Design with Initial and Always blocks
  • Chapter 3: Verilog Syntax Details
    • 3.1 Structural Data Types: wire and reg
    • 3.2 Behavioral Data Types: integer, real, and time
    • 3.3 Number Syntax
    • 3.4 Behavioral Design with blocking and non-blocking statements
    • 3.5 Arrays, Vectors, and Memories
    • 3.6 Operators
  • Chapter 4: Verilog Design Flow
    • Step 1: Create RTL Design Models and Behavioral Test Bench Code
    • Step 2: Functionally Simulate your Register-Transfer-Level Design
    • Step 3: Convert RTL-level files to a Gate-level model with a Synthesizer
    • Step 4: Perform Gate Level simulations with FPGA or ASIC libraries
    • Optional Step: Gate-level simulation with SDF timing information
Info site for timing diagrams